> For the complete documentation index, see [llms.txt](https://validium.gitbook.io/docs/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://validium.gitbook.io/docs/components/compiler/specification/instructions/evm/memory.md).

# Memory

***

### MLOAD <a href="#mload" id="mload"></a>

Original [EVM](https://www.evm.codes/#51?fork=shanghai) instruction.

Heap memory load operation is modeled with a native EraVM instruction.

#### LLVM IR <a href="#llvm-ir" id="llvm-ir"></a>

```llvm
%value = load i256, ptr addrspace(1) %pointer, align 1
```

[The LLVM IR generator code](https://github.com/matter-labs/era-compiler-llvm-context/blob/main/src/eravm/evm/memory.rs#L15) is common for Yul and EVMLA representations.

[LLVM IR instruction documentation](https://releases.llvm.org/15.0.0/docs/LangRef.html#load-instruction)

#### [EraVM Assembly](https://docs.zksync.io/zk-stack/components/compiler/specification/instructions/evm/memory#eravm-assembly) <a href="#eravm-assembly" id="eravm-assembly"></a>

```llvm
ld.1    r1, r2
```

See [EraVM instruction: `st.1`](https://matter-labs.github.io/eravm-spec/spec.html#LoadDefinition)

### MSTORE <a href="#mstore" id="mstore"></a>

Original [EVM](https://www.evm.codes/#52?fork=shanghai) instruction.

Heap memory load operation is modeled with a native EraVM instruction.

#### LLVM IR <a href="#llvm-ir-1" id="llvm-ir-1"></a>

```llvm
store i256 128, ptr addrspace(1) inttoptr (i256 64 to ptr addrspace(1)), align 1
```

[The LLVM IR generator code](https://github.com/matter-labs/era-compiler-llvm-context/blob/main/src/eravm/evm/memory.rs#L38) is common for Yul and EVMLA representations.

[LLVM IR instruction documentation](https://releases.llvm.org/15.0.0/docs/LangRef.html#store-instruction)

#### [EraVM Assembly](https://docs.zksync.io/zk-stack/components/compiler/specification/instructions/evm/memory#eravm-assembly-1) <a href="#eravm-assembly-1" id="eravm-assembly-1"></a>

```llvm
st.1    r1, r2
```

See [EraVM instruction: `st.1`](https://matter-labs.github.io/eravm-spec/spec.html#StoreDefinition)

### [MSTORE8](https://docs.zksync.io/zk-stack/components/compiler/specification/instructions/evm/memory#mstore8) <a href="#mstore8" id="mstore8"></a>

Original [EVM](https://www.evm.codes/#53?fork=shanghai) instruction.

#### [LLVM IR](https://docs.zksync.io/zk-stack/components/compiler/specification/instructions/evm/memory#llvm-ir-2) <a href="#llvm-ir-2" id="llvm-ir-2"></a>

```llvm
define void @__mstore8(i256 addrspace(1)* nocapture nofree noundef dereferenceable(32) %addr, i256 %val) #2 {
entry:
  %orig_value = load i256, i256 addrspace(1)* %addr, align 1
  %orig_value_shifted_left = shl i256 %orig_value, 8
  %orig_value_shifted_right = lshr i256 %orig_value_shifted_left, 8
  %byte_value_shifted = shl i256 %val, 248
  %store_result = or i256 %orig_value_shifted_right, %byte_value_shifted
  store i256 %store_result, i256 addrspace(1)* %addr, align 1
  ret void
}
```

[The LLVM IR generator code](https://github.com/matter-labs/era-compiler-llvm-context/blob/main/src/eravm/evm/memory.rs#L62) is common for Yul and EVMLA representations.

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